Huawei Focuses on Speed to Overcome US Chip Sanctions

• Huawei claims its new Kirin smartphone chip launching later this year will improve power efficiency by 41% and raise peak operating speed by nearly 13% compared to single-layer designs, though production yields and cost comparisons were not disclosed
• The approach requires new electronic design automation (EDA) tools and better heat management solutions, presenting significant technical barriers alongside concerns about overheating and production costs
• Nvidia CEO Jensen Huang downplayed the threat to TSMC, noting that advanced die stacking and 3D packaging technologies have been used by the industry leader for nearly a decade

Huawei Focuses on Speed to Overcome US Chip Sanctions

Key Development:

Huawei unveiled a new chip design principle called "Tau Scaling Law" aimed at circumventing US semiconductor sanctions by focusing on transmission speed rather than miniaturization. The approach uses "LogicFolding" technology to stack logic, analog, and memory circuits in tightly connected structures.

Strategic Context:

China has been blocked from importing ASML's advanced extreme ultraviolet (EUV) lithography machines since 2019, preventing Chinese chipmakers from competing with leaders like TSMC in advanced manufacturing processes. Huawei executive He Tingbo acknowledged the company faces constraints from both Moore's Law limitations and US sanctions.

Technical Claims:

Huawei's upcoming Kirin smartphone chip, launching later this year, will be the first to use LogicFolding architecture. The company projects:

• 41% improvement in power efficiency
• Nearly 13% increase in peak operating speed versus single-layer designs

Industry Skepticism:

Nvidia CEO Jensen Huang dismissed the breakthrough claim, noting TSMC has used die stacking and 3D packaging for nearly a decade. Industry experts and Bernstein analysts highlighted existing challenges including:

• Overheating risks from increased power density
• Production yield and cost barriers
• Need for new electronic design automation (EDA) tools from vendors like Cadence and Synopsys

Market Impact:

Competitors including TSMC, SK Hynix, and Samsung already employ advanced 3D stacking technologies. Omdia analyst Lian Jye Su noted there's "nothing concrete that can be independently verified or benchmarked" against competitors. The technology's commercial viability remains uncertain pending the Kirin chip launch and independent verification of performance claims.